The present invention relates to a PLL circuit and a control method thereof. For example, the present invention relates to a PLL circuit suitable for generating an oscillating signal with a high accuracy by reducing a phase offset, and a control method thereof.
PLL (Phase Locked Loop) circuits are mounted as oscillating circuits on various semiconductor devices. A PLL circuit is a circuit that controls the frequency of an output signal so that the phase of a reference signal and the phase of the output signal match each other.
In the PLL circuit, a phase offset may occur due to variations in the current that flows when a charge switch and a discharge switch, which constitute a charge pump, are turned on. The term “phase offset” used herein refers to a steady phase difference between the reference signal and the output signal when the PLL circuit is locked.
A solution to this problem is disclosed in the specification of U.S. Pat. No. 7,511,543 B2. A PLL circuit disclosed in the specification of U.S. Pat. No. 7,511,543 B2 reduces a phase offset by adjusting an output current of a charge pump based on a difference in pulse width between a down signal and an up signal which are output from a replica of a phase comparator when the PLL circuit is locked.